Improvements in NAND flash memory technology have led to reduced solid state device geometries and increased bit density of nonvolatile NAND flash memories. This has lead to, accordingly, an increase in error rates of data decoded from such memories. One type of error correction code commonly employed in nonvolatile memory storage modules are low-density parity-check (LDPC) codes. An LDPC code is a linear error correcting code having a parity check matrix with a small number of non-zero elements in each row and column.
The power of LDPC codes resides in the ability of the decoder to exploit so-called ‘soft’ information on the stored data. For example, in single level cell (SLC) memory, two charge states represent the two possible states: ‘0’ and ‘1’, of the cells within the NAND chips. In MLC memory, four charge states represent the 4 possible states: ‘00’, ‘01’, ‘10’ and ‘11’, TLC memory has eight charge states, and so on. When data is stored, charge programming variations cause the programmed charge state to be an analogue quantity which varies according to a statistical distribution rather than a discrete value. Further, charge distributions of different states may overlap and stored charge may drift over time. To read the data, a voltage threshold is applied to determine in which charge state the cell lies, providing a binary result (above or below the threshold). A single threshold suffices for SLC to provide a 0/1 result and for MLC and TLC results from multiple thresholds provide multiple bits. To determine more accurate information on charge state, further reads known as ‘soft reads’ provide extra bits of soft information which are expressed by a log likelihood ratio (LLR) which LDPC decoders can make use of to perform decoding. The LLR attributed to a bit is representative of the probability that the charge state value read corresponds to a ‘0’ or a ‘1’. The sign of the LLR typically provides the bit estimation (i.e. positive LLR corresponds to ‘1’ and negative LLR corresponds to ‘0’ according to one convention). The magnitude of the LLR provides the reliability of the estimation (i.e. |LLR|=0 means that the estimation is completely unreliable and |LLR|=00 means that the estimation is completely reliable and the bit value is known). The decoding performance of the soft decision LDPC decoder depends on the accuracy of the LLR values.
Reading soft information from the NAND memory array requires multiple reads at varying threshold voltages. Due to the high memory cell density in flash memory arrays, the reads from a cell in a memory array may be influenced by the level of neighboring bits in the page. This degrades the quality of the read. In particular, there are ‘bad’ sequences of levels which are more likely to lead to errors when the page is read. Further, performing multiple reads is time consuming and has a severe negative impact on the performance of the flash memory controller. As such, there is a long-felt need to obtain LLR data with improved accuracy to obtain quality LLR data that will be useful in the decoding process.